Introduction

In the Nanosecond Economy, the CPU is the bottleneck. A CPU is a “Juggler”: It handles thousands of tasks (OS, Network, Logic) by switching between them very fast. An FPGA is an “Assembly Line”: It does one thing, perfectly, in parallel, with zero interruptions.

This lesson explores why we burn custom silicon to save 700 nanoseconds.

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The Physics: Tick-to-Trade (T2T)

The Metric: Time from “First Bit of Market Data In” to “First Bit of Order Out”.

• Software (C++): ~2-5 microseconds.
• FPGA (Hardware): ~40-100 nanoseconds.

Physics: Software pays the “von Neumann Tax”:

1. Interrupt fires.
2. Context Switch to Kernel Mode.
3. Copy Packet to RAM.
4. Context Switch to User Mode.
5. CPU reads RAM into Cache (Cache Miss?).
6. CPU executes instruction.

FPGA pays Zero Tax. The electrons flow through the logic gates like water through a pipe.

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Deep Dive: Pipelining (The Assembly Line)

How does an FPGA process 100 Million Insert messages per second? Pipelining.

The Physics: Imagine a packet takes 100 clock cycles to process.

• CPU: Must finish Packet A before starting Packet B. Throughput = 1/100.
• FPGA: Splits the task into 100 stages.
  • Cycle 1: Stage 1 processes Packet A.
  • Cycle 2: Stage 2 processes Packet A. Stage 1 processes Packet B.
  • Result: Throughput = 1 packet per cycle. Massive Parallelism.

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Architecture: Hybrid Systems (Solarflare)

Most firms don’t just use FPGA. They use SmartNICs (e.g., Solarflare X3522). The FPGA sits on the Network Card.

1. Filtering: FPGA drops 99% of “Noise” packets.
2. Forwarding: Sends only “Signal” packets to the CPU over PCIe.
3. Result: CPU load drops; crucial latency improves.

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Code: Verifying an Order (Verilog)

In Software, if (price > limit) is compiled to assembly. In Hardware, if (price > limit) allows electrons to flow to the “Buy” wire.

module OrderTrigger (
    input wire clk,
    input wire [31:0] market_price,
    input wire [31:0] limit_price,
    output reg buy_signal
);

    always @(posedge clk) begin
        // The comparison happens physically in 1 clock cycle (3ns)
        if (market_price < limit_price) begin
            buy_signal <= 1'b1;
        end else begin
            buy_signal <= 1'b0;
        end
    end

endmodule

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Practice Exercises

Exercise 1: The Jitter (Beginner)

Scenario: Measure latency of 1000 orders. Software: Min 5us, Max 50us (OS Jitter). FPGA: Min 80ns, Max 82ns (Deterministic). Lesson: FPGA wins on Consistency (Standard Deviation).

Exercise 2: Throughput Math (Intermediate)

Scenario: FPGA Clock = 300 MHz (3.3ns per cycle). Pipeline: Can accept 1 packet every cycle. ** Throughput:** $300,000,000 \text{ packets/sec}$. Bandwidth: If packet is 64 bytes: $300M \times 64B \approx 19.2 \text{ GB/s}$. (Line Rate 25Gbps is saturated).

Exercise 3: Development Cost (Advanced)

Scenario: A bug is found in algo logic. Software: Fix + Compile = 30 seconds. FPGA: Fix + Synthesis + Place & Route = 4 to 12 hours. Tradeoff: FPGAs are inflexible. Only use them for logic that rarely changes (e.g., Feed Parsing, Risk Checks).

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Knowledge Check

1. What is the “von Neumann Tax”?
2. Why is FPGA latency “Deterministic”?
3. What is Pipelining?
4. Why is FPGA development slower than C++?
5. What is a SmartNIC?

Answers

1. Memory Access. Fetching instructions and data from RAM dominates execution time.
2. No OS. No scheduling, no interrupts. Every clock cycle does exactly the same work.
3. Parallel Stages. Processing different parts of multiple packets simultaneously.
4. Synthesis. Compiling code into physical circuit layout is mathematically complex (NP-Hard).
5. FPGA + NIC. A network card with a programmable chip for offloading tasks.

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Summary

• Software: Juggling.
• FPGA: Assembly Line.
• Latency: Nanoseconds.

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